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6.2.7 RESET OPERATIONS
High Z
STS(R)
V OL
V IH
RP#(P)
V IL
High Z
STS(R)
V OL
V IH
RP#(P)
V IL
2.7/3.3V
LHF16KTV
t PLPH
(A)Reset During Read Array Mode
t PLRH
t PLPH
(B)Reset During Block Erase, Full Chip Erase, (Multi) Word/Byte Write
or Block Lock-Bit Configuretion
45
V CC
V IL
t 23VPH
V IH
RP#(P)
V IL
(C)V CC Power Up Timing
Figure 21. AC Waveform for Reset Operation
Reset AC Specifications
V CC =2.7V
V CC =3.3V
Symbol
Parameter
Notes
Min.
Max.
Min.
Max.
Unit
t PLPH
RP# Pulse Low Time
(If RP# is tied to V CC , this specification is
not applicable)
100
100
ns
t PLRH
RP# Low to Reset during Block Erase,
Full Chip Erase, (Multi) Word/Byte Write
1,2
21.5
21.1
μs
or Block Lock-Bit Configuration
t 23VPH
V CC at 2.7V to RP# High
V CC at 3.0V to RP# High
3
100
100
ns
NOTES:
1. If RP# is asserted while a block erase, full chip erase, (multi) word/byte write or block lock-bit configuration
operation is not executing, the reset will complete within 100ns.
2. A reset time, t PHQV , is required from the latter of STS going High Z or RP# going high until outputs are valid.
3. When the device power-up, holding RP# low minimum 100ns is required after V CC has been in predefined range
and also has been in stable there.
Rev. 2.0
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